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Topic Id:
ID topic:
245
Partner Email:
alsu@cc.ttu.ee
Project Title:
Synthesis of Digital Systems from Hierarchical and Parallel Specifications
Abstract:
It is known that most models of computation include components with state, where behavior is given as a sequence of state transitions. The latter can be encapsulated in reusable modules at a specification level. The modules can be activated hierarchically and in parallel. Besides they might be recursive. Prior knowledge required: Advanced Digital System Design, FPGA Based System Design, VHDL
Advisor:
Alexander Sudnitson
Link:
Degree:
Master
Keywords:
