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Topic Id:
ID topic:
81
Partner Email:
anne.villems@ut.ee
Project Title:
FPGA Based Design of Digital Device
Abstract:
This bachelor work represents a process of designing at the Registry Transfer Level of the device counting least common multiplier of two integers. Development should made using hardware description language VHDL. The simulating environment Active-HDL Student Edition and Xilinx program Webpack ISE (Student Edition) should be used. Prior knowledge required: FPGA Based Design Digital System Design VHDL
Advisor:
Anne Villems
Link:
Degree:
Bachelor
Keywords:
